Verification

There are two aspects to checking that the CPU implementation is correct: checking that the behaviour specification complies with the RISC-V specification; and checking that the design behaviour matches the specification.

The plan for designing and testing the CPU is as follows:

  • Design the modules as per the specification/design outline, and write some preliminary testbenches

    • Design the unprivileged subset first (ignoring traps and Zicsr instructions). This can be used to test most of the data path and control unit for most instruction types.

    • Add in support for exceptions

    • Add in support for interrupts

Next, the design will be compared against the specification:

  • Create a testing plan for functional verification, and develop a set of testbenches to implement this plan.

  • Create a formal verification plan, and implement it for the design.

Finally, the design will be compared against expected RISC-V behaviour (which will checking the specification complies with RISC-V)

  • Compare the behaviour of the design with expected behaviour using a set of RISC-V unit tests.