Notes

// In this example, only the rdata (read data) line
// is included for simplicity, to focus on the output
// side of the bus. The interface can be modified to
// include other lines such as wdata, clk,
// write_en etc. as required.
//
// This example assumes there is one bus host (the
// module instantiating the bus), communicating with
// multiple devices.
//
// A limitation of this method is that the number of
// devices on the bus must be specified in advance.
// This is manageable if the number of devices is
// relatively small.
interface bus #(
   parameter NUM_DEVICES = 2
) (
   output bit [31:0] rdata,
   input bit [31:0]  addr,
   // other bus lines as required...
);

   // Inside the bus, each device gets its own
   // rdata line, called dev_rdata.
   bit [31:0] dev_rdata[NUM_DEVICES];

   // Make the output rdata signal here by ORing
   // together all the device dev_rdata signals.
   // This is all internal to the interface, and
   // reduces duplication in the modules using the
   // bus.
   always_comb begin
      rdata = 0;
      for (int n = 0; n < NUM_DEVICES; n++) begin
	 rdata |= dev_rdata[n];
      end
   end

   // Each device must have its own modport, to link
   // each to a different dev_rdata line.
   generate
      for (genvar n = 0; n < NUM_DEVICES; n++) begin: dev
	 modport device (
	    // Make the device's dev_rdata line appear to
	    // have the name rdata from the device's point
	    // of view.
	    output .rdata(dev_rdata[n]),
	    input  addr
	 );
      end
   endgenerate

   // If the bus need a bus controller modport, this
   // can be added here (

endinterface: bus

// Both device modules take the bus as a port.
// In this example, dev1 sets its own rdata to
// non-zero only for addr == 0. The modport
// is specified in the device instantiation
// (see modport), so it is not also included
// here.
module dev1(bus bus);
   always_comb begin
      if (bus.addr == 0)
      	 rdata = 10;
      else
         rdata = 0;
   end
endmodule

// Device 2 sets rdata to non-zero only for
// addr == 1. In the interface logic, the
// rdata lines from dev1 and dev2 are ORed
// together to make the rdata line exposed
// in the module mod below.
module dev2(bus bus);
   always_comb begin
      if (bus.addr == 1)
      	 rdata = 20;
      else
         rdata = 0;
   end
endmodule

module mod();

   // Mod can set the address and
   // then read data from rdata, which
   // comes from one of the devices. In
   // this example, there is no device
   // select signal -- the device could
   // know when it should return data
   // based on the address.
   bit [31:0] addr, rdata

   // Instantiate the bus
   bus #(NUM_DEVICES=2) bus(.rdata, .addr);

   // Instantiate devices and connect them to the bus.
   // Note the use of the label name dev to access the
   // modport.
   dev1 dev1(.bus(bus.dev[0].device))
   dev2 dev2(.bus(bus.dev[1].device))

endmodule